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CS53L32A Low Voltage, Stereo A/D Converter
FEATURES
20-Pin TSSOP package 1.8 V to 3.3 V supply 24-bit conversion / 96 kHz sample rate 98 dB dynamic range at 3 V supply -88 dBFS THD+N Low power consumption
- 11 mW at 1.8 V
DESCRIPTION
The CS53L32A is a highly integrated, 24-bit, 96 kHz audio ADC providing stereo analog-to-digital converters using delta-sigma conversion techniques. This device includes volume control and line level inputs in a 20-pin TSSOP package. The CS53L32A is based on delta-sigma modulation allowing infinite adjustment of the sample rate between 2 kHz and 100 kHz simply by changing the master clock frequency. The CS53L32A contains adjustable analog gain, a 2:1 input mux, and digital attenuation. The CS53L32A operates from a +1.8 V to +3.3 V supply. These features are ideal for portable MP3 players, MD recorders/players, digital camcorders, PDAs, set-top boxes, and other portable systems that require extremely low power consumption in a minimum of space.
Up to 32 dB gain
- 20 dB gain step - 12 dB variable input gain, 1 dB steps - Changes made at zero crossings
Stereo inputs Digital volume control
- 96 dB attenuation, 1 dB step size - Mute - Soft ramping
2:1 Input mux
ORDERING INFORMATION
CS53L32A-KZ 20-pin TSSOP -10 to 70 C CS53L32A-KZZ 20-pin TSSOP -10 to 70 C CS53L32A-BZ 20-pin TSSOP -40 to 85 C CDB53L32A Evaluation Board Lead free
II
SCL/CCLK/ ChSEL SDA/CDIN/DIF RST VA
VL
AD0/CS/DIV
Control Port AIN_L1 Serial Port
LRCK SCLK SDOUT
Attenuator 0-96 dB Attenuator 0-96 dB
ADC
Digital Filters
Gain
AIN_L2
ADC
AIN_R1
Gain
AIN_R2
GND VQ
MCLK
FILT+
REF_GND
AFLTL
AFLTR
http://www.cirrus.com
Copyright (c) Cirrus Logic, Inc. 2004 (All Rights Reserved)
OCT `04 DS513F1
CS53L32A
TABLE OF CONTENTS
1. CHARACTERISTICS/SPECIFICATIONS ................................................................................. 4 ANALOG CHARACTERISTICS ................................................................................................ 4 ANALOG CHARACTERISTICS ................................................................................................ 5 POWER AND THERMAL CHARACTERISTICS....................................................................... 8 DIGITAL CHARACTERISTICS ................................................................................................. 9 ABSOLUTE MAXIMUM RATINGS ........................................................................................... 9 RECOMMENDED OPERATING CONDITIONS ....................................................................... 9 SWITCHING CHARACTERISTICS ........................................................................................ 10 SWITCHING CHARACTERISTICS - CONTROL PORT - TWO WIRE MODE....................... 12 SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE.................................... 13 2. TYPICAL CONNECTION DIAGRAM .................................................................................... 14 3. REGISTER QUICK REFERENCE .......................................................................................... 15 3.1 I/O and Power Control (address 01h) ............................................................................... 15 3.2 Interface Control (address 02h) ........................................................................................ 15 3.3 Analog I/O Control (address 03h) ..................................................................................... 16 3.4 Left Channel Digital Volume Control (address 04h).......................................................... 17 3.5 Right Channel Digital Volume Control (address 05h) ....................................................... 17 3.6 Analog Gain Control (address 06h) .................................................................................. 17 3.7 Clip Detection Status (address 07h) ................................................................................. 17 4. REGISTER DESCRIPTION .................................................................................................... 18 4.1 Gain Enable ...................................................................................................................... 18 4.2 Analog Input Multiplexer ................................................................................................... 18 4.3 Power-Down ..................................................................................................................... 19 4.4 Control Port Enable........................................................................................................... 19 4.5 Master Clock Divide .......................................................................................................... 20 4.6 Master Clock Ratio............................................................................................................ 20 4.7 Master Mode ..................................................................................................................... 21 4.8 Digital Interface Format..................................................................................................... 21 4.9 Left/Right Channel Mute ................................................................................................... 22 4.10 Soft Ramp and Zero Cross Enable ................................................................................. 22 4.11 Independent Volume Control Enable .............................................................................. 23 4.12 Left Channel Volume = Right Channel Volume .............................................................. 24 4.13 High-Pass Filter Freeze .................................................................................................. 24 4.14 Volume Control ............................................................................................................... 25 4.15 Left/Right Analog Gain.................................................................................................... 26 4.16 Clip Detection.................................................................................................................. 26 5. PIN DESCRIPTION ................................................................................................................. 27 6. PIN DESCRIPTION ................................................................................................................. 28 6. PIN DESCRIPTION ................................................................................................................. 28 6. APPLICATIONS ...................................................................................................................... 30 6.1 Grounding and Power Supply Decoupling ....................................................................... 30 6.2 Oversampling Modes ....................................................................................................... 30 6.3 Recommended Power-up Sequence ............................................................................... 30 7. CONTROL PORT INTERFACE ............................................................................................. 30 7.1 SPI Mode ......................................................................................................................... 30 7.2 Two Wire Mode ................................................................................................................ 31 7.3 Memory Address Pointer (MAP) ....................................................................................... 31 8. PARAMETER DEFINITIONS .................................................................................................. 38 9. REFERENCES ........................................................................................................................ 38 10. PACKAGE DIMENSIONS ..................................................................................................... 39 11. CHANGE HISTORY .............................................................................................................. 40
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LIST OF FIGURES
Figure 1. SCLK to LRCK and SDOUT, Slave Mode ..................................................................... 11 Figure 2. SCLK to LRCK and SDOUT, Master Mode ................................................................... 11 Figure 3. Relationship Required Between LRCK and MCLK in Slave Mode ................................ 11 Figure 4. Control Port Timing - Two Wire Mode............................................................................ 12 Figure 5. Control Port Timing - SPI Mode ..................................................................................... 13 Figure 6. Typical Connection Diagram.......................................................................................... 14 Figure 7. Control Port Timing, SPI Mode ...................................................................................... 32 Figure 8. Control Port Timing, Two Wire Mode............................................................................. 32 Figure 9. Base-Rate Stopband Rejection...................................................................................... 33 Figure 10. Base-Rate Transition Band.......................................................................................... 33 Figure 11. Base-Rate Transition Band (Detail) ............................................................................. 33 Figure 12. Base-Rate Passband Ripple........................................................................................ 33 Figure 13. High-Rate Stopband Rejection .................................................................................... 33 Figure 14. High-Rate Transition Band........................................................................................... 33 Figure 15. High-Rate Transition Band (Detail) .............................................................................. 34 Figure 16. High-Rate Passband Ripple......................................................................................... 34 Figure 17. Line Input Test Circuit .................................................................................................. 34 Figure 18. CS53L32A Control Port Mode - Serial Audio Format 0 (I2S) ....................................... 34 Figure 19. CS53L32A Control Port Mode - Serial Audio Format 1 ............................................... 35 Figure 20. CS53L32A Control Port Mode - Serial Audio Format 3 ............................................... 35 Figure 21. CS53L32A Control Port Mode - Serial Audio Format 4 ............................................... 35 Figure 22. CS53L32A Control Port Mode - Serial Audio Format 5 ............................................... 36 Figure 23. CS53L32A Control Port Mode - Serial Audio Format 6 ............................................... 36 Figure 24. CS53L32A Stand-Alone Mode - Serial Audio Format 0 (I2S) ...................................... 36 Figure 25. CS53L32A Stand-Alone Mode - Serial Audio Format 1............................................... 37
LIST OF TABLES
Table 1. Analog Input Options....................................................................................................... 18 Table 2. Power-Down Enable ....................................................................................................... 19 Table 3. Control Port Enable......................................................................................................... 19 Table 4. Master Clock Divide Select ............................................................................................. 20 Table 5. MCLK/LRCK Ratios ........................................................................................................ 20 Table 6. Master/Slave Mode Selection ......................................................................................... 21 Table 7. Digital Interface Format................................................................................................... 21 Table 8. Left/Right Channel Mute Enable ..................................................................................... 22 Table 9. Analog Volume Control ................................................................................................... 23 Table 10. Digital Volume Control .................................................................................................. 23 Table 11. Independent Volume Control Enable ............................................................................ 23 Table 12. High-Pass Filter Enable ................................................................................................ 24 Table 13. Example Volume Settings ............................................................................................. 25 Table 14. Example Gain Settings.................................................................................................. 26 Table 15. Clip Detection Status Bits.............................................................................................. 26 Table 16. Common Clock Frequencies......................................................................................... 28 Table 17. Digital Interface Format - DIF (Stand-Alone Mode)....................................................... 28 Table 18. Channel Select Options ................................................................................................ 28 Table 19. Revision Table .............................................................................................................. 40
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1. CHARACTERISTICS/SPECIFICATIONS
ANALOG CHARACTERISTICS (TA = 25 C; Logic "1" = VL = 1.8 V; Logic "0" = GND = 0 V; MCLK = 12.288 MHz; Fs for Base-rate Mode = 48 kHz, SCLK = 3.072 MHz, Measurement Bandwidth 10 Hz to 20 kHz, unless otherwise specified. Fs for High-Rate Mode = 96 kHz, SCLK = 6.144 MHz, Measurement Bandwidth 10 Hz to 20 kHz, unless otherwise specified. Input signal is a 997 Hz sine wave.)
Base-rate Mode Parameter Dynamic Range A-weighted unweighted Symbol Min 88 85 Typ 93 90 -88 -70 -30 -86 -68 -28 Max -83 High-rate Mode Min 89 86 Typ 94 91 -88 -71 -31 -86 -68 -28 Max -83 Unit dB dB dB dB dB dB dB dB
CS53L32A-KZ/KZZ Analog Input Characteristics for VA = 1.8 V
Total Harmonic Distortion + Noise (Note 1) THD+N 18 to 24-Bit -1 dB -20 dB -60 dB 16-Bit -1 dB -20 dB -60 dB Dynamic Range (PGA on)* 0 dB Gain A-weighted unweighted 12 dB Gain A-weighted unweighted THD+N Total Harmonic Distortion + Noise (PGA on)* (Note 1) 0 dB Gain 18 to 24-Bit -1 dB 12 dB Gain 18 to 24-Bit -1 dB Dynamic Range A-weighted unweighted
-
90 87 85 82
-
-
89 86 86 83
-
dB dB dB dB
91 88 -
85 83 96 93 -88 -73 -33 -86 -68 -28
-83 -
93 90 -
84 82 98 95 -85 -75 -35 -83 -65 -28
-80 -
dB dB dB dB dB dB dB dB dB dB
CS53L32A-KZ/KZZ Analog Input Characteristics for VA = 3.0 V
Total Harmonic Distortion + Noise (Note 1) THD+N 18 to 24-Bit -1 dB -20 dB -60 dB 16-Bit -1 dB -20 dB -60 dB Dynamic Range (PGA on)* 0 dB Gain A-weighted unweighted 12 dB Gain A-weighted unweighted
-
93 90 88 85
-
-
92 89 89 86
-
dB dB dB dB
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ANALOG CHARACTERISTICS (CONTINUED)
Base-rate Mode Parameter Symbol Min Typ Max THD+N Total Harmonic Distortion + Noise (PGA on)* (Note 1) 0 dB Gain 18 to 24-Bit -1 dB 12 dB Gain 18 to 24-Bit -1 dB Interchannel Isolation Interchannel Gain Mismatch Offset Error Full Scale Input Voltage Gain Drift Input Resistance Input Capacitance with High Pass Filter 1 kHz High-rate Mode Min Typ Max Unit
-5% 10 -
78 73 90 0.1 VA/3.6 100 93 90 -88 -70 -30 -86 -68 -28 90 87 85 82
0 +5% 15 -81 -
-5% 10 87 84 -
77 76 90 0.1 100 94 91 -88 -71 -31 -86 -68 -28 89 86 86 83
0 15 -81 -
dB dB dB dB LSB Vrms ppm/C k pF dB dB dB dB dB dB dB dB dB dB dB dB
CS53L32A-KZ/KZZ Analog Input Characteristics for VA=1.8 V - 3.3 V
VA/3.6 +5%
CS53L32A-BZ Analog Input Characteristics for VA = 1.8 V
Dynamic Range Total Harmonic Distortion + Noise 18 to 24-Bit A-weighted unweighted (Note 1) THD+N -1 dB -20 dB -60 dB -1 dB -20 dB -60 dB 0 dB Gain A-weighted unweighted 12 dB Gain A-weighted unweighted 86 83 -
16-Bit
Dynamic Range (PGA on)*
Total Harmonic Distortion + Noise (PGA on)* THD+N (Note 1) 0 dB Gain 18 to 24-Bit -1 dB 12 dB Gain 18 to 24-Bit -1 dB
89 86
85 83 96 93
-
91 88
84 82 98 95
-
dB dB dB dB
CS53L32A-BZ Analog Input Characteristics for VA = 3.0 V
Dynamic Range A-weighted unweighted
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Base-rate Mode Parameter Total Harmonic Distortion + Noise 18 to 24-Bit Symbol (Note 1) THD+N -1 dB -20 dB -60 dB -1 dB -20 dB -60 dB 0 dB Gain A-weighted unweighted 12 dB Gain A-weighted unweighted THD+N Total Harmonic Distortion + Noise (PGA on)* (Note 1) 0 dB Gain 18 to 24-Bit -1 dB 12 dB Gain 18 to 24-Bit -1 dB Min Typ -88 -73 -33 -86 -68 -28 Max -81 High-rate Mode Min Typ -85 -75 -35 -83 -65 -28 Max -78 Unit dB dB dB dB dB dB
16-Bit
Dynamic Range (PGA on)* 93 90 88 85 92 89 89 86 dB dB dB dB
-
78 73
-
-
77 76
-
dB dB
* PGA = Programmable Gain Amplifier CS53L32A-BZ Analog Input Characteristics for VA=1.8 - 3.3V
Interchannel Isolation Interchannel Gain Mismatch Offset Error Full Scale Input Voltage Gain Drift Input Resistance Input Capacitance with High Pass Filter 1 kHz -7% 10 (Note 3) (Note 3) (Note 4) (Note 5) tgd tgd 0 -0.08 27.5 -60.3 90 0.1 VA/3.6 100 1.0 10/Fs 0 +7% 15 0.3 23.5 0.03 -7% 10 0 64.1 -48.4 90 0.1 100 1.0 2.7/Fs 0 15 0.3 47.5 0 0.007 dB dB LSB Vrms ppm/C k pF dB dB kHz dB kHz dB s s
VA/3.6 +7%
Programmable Gain Characteristics
Gain Step Size Absolute Gain Step Error
A/D Decimation Filter Characteristics (Note 2)
Passband Passband Ripple Stopband Stopband Attenuation Group Delay (Fs = Output Sample Rate) Group Delay Variation vs. Frequency +0.17 -0.09
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Base-rate Mode Parameter Symbol (Note 2) (Note 2) (Note 2) Min Typ 3.7 24.2 10 Max 0.17 High-rate Mode Min Typ 3.7 24.2 10 Max 0.09 Unit Hz Hz Degree dB
High Pass Filter Characteristics
Frequency Response Phase Deviation Passband Ripple -3 dB -0.1 dB @ 20 Hz
Notes: 1. Referenced to typical full-scale input voltage (0.5 Vrms). 2. Filter response is not tested but is guaranteed by design. 3. Filter characteristics scale with output sample rate. For output sample rates, Fs, other than 48 kHz, the 0.01 dB passband edge is 0.4535x Fs and the stopband edge is 0.625x Fs. 4. The analog modulator samples the input at 6.144 MHz for an Fs equal to 48 kHz. There is no rejection of input signals which are multiples of the sampling frequency (n x 6.144 MHz 21.8 kHz where n = 0,1,2,3...). 5. Group delay for Fs = 48 kHz, tgd = 10/48 kHz = 208 s.
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CS53L32A
POWER AND THERMAL CHARACTERISTICS
Base-Rate Mode Parameters Symbol VA=1.8 V VL=1.8 V VA=1.8 V VL=1.8 V VA=3.0 V VL=3.0 V VA=3.0 V VL=3.0 V All Supplies=1.8 V All Supplies=3.0 V JA (1 kHz) PSRR (60 Hz) IA ID_IO IA ID_IO IA ID_IO IA ID_IO Min Typ 6.0 150 100 0 9 260 250 0 11 28 75 60 40 Max 12 31 High-Rate Mode Min Typ 7.6 300 250 0 11.5 520 500 0 14.5 36 75 60 40 Max 16 40 Units mA A A A mA A A A mW mW C/Watt dB dB
Power Supplies
Power Supply CurrentNormal Operation Power Supply CurrentPower Down Mode (Note 6) Power Supply CurrentNormal Operation Power Supply CurrentPower Down Mode Total Power DissipationNormal Operation
Package Thermal Resistance Power Supply Rejection Ratio (Note 7)
Notes: 6. Power Down Mode is defined as the chip being held in reset with MCLK running. To lower power consumption further, remove MCLK. 7. Valid with the recommended capacitor values on FILT+ and VQ as shown in Figure 6.
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DIGITAL CHARACTERISTICS (TA = 25 C; VL = 1.7 V - 3.6 V; GND = 0 V)
Parameters High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage Low-Level Output Voltage Leakage Current Input Capacitance Symbol VIH VIL VOH VOL Iin Min 0.7*VL 0.7*VL Typ 8 Max 0.3*VL 0.3*VL 10 Units V V V V A pF
ABSOLUTE MAXIMUM RATINGS (GND = 0 V; all voltages with respect to ground.)
Parameters DC Power Supplies: Positive Analog Digital I/O Symbol VA VL Iin VIND TA Tstg Min -0.3 -0.3 -0.3 -55 -65 Max 4.0 4.0 10 VL+0.4 125 150 Units V V mA V C C
Input Current, Any Pin Except Supplies Digital Input Voltage Ambient Operating Temperature (power applied) Storage Temperature
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS (GND = 0V; all voltages with respect to ground.)
Parameters Ambient Temperature DC Power Supplies: Positive Analog Digital I/O Symbol TA VA VL Min -10 1.7 1.7 Typ Max 70 3.6 3.6 Units C V V
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CS53L32A
SWITCHING CHARACTERISTICS (TA = -10 to 70 C; VA = 1.7 V - 3.6 V; Inputs: Logic 0 = GND,
Logic 1 = VL, CL = 20 pF) Parameters Input Sample Rate MCLK Pulse Width High MCLK Pulse Width Low MCLK Pulse Width High MCLK Pulse Width Low MCLK Pulse Width High MCLK Pulse Width Low MCLK Pulse Width High MCLK Pulse Width Low MCLK Pulse Width High MCLK Pulse Width Low Base Rate Mode High Rate Mode MCLK/LRCK = 1024 MCLK/LRCK = 1024 MCLK/LRCK = 768 MCLK/LRCK = 768 MCLK/LRCK = 512 MCLK/LRCK = 512 MCLK / LRCK = 384 or 192 MCLK / LRCK = 384 or 192 MCLK / LRCK = 256 or 128 MCLK / LRCK = 256 or 128 Symbol Fs Fs Min 2 50 8 8 10 10 15 15 21 21 31 31 Typ Max 50 100 Units kHz kHz ns ns ns ns ns ns ns ns ns ns
Master Mode
SCLK Falling to LRCK Edge SCLK Falling to SDOUT Valid SCLK Duty Cycle tslrd tsdo -20 0 40 50 20 20 60 ns ns %
Slave Mode
LRCK Duty Cycle Rise Time of Both LRCK and SCLK Fall Time of Both LRCK and SCLK SCLK Period Base Rate Mode High Rate Mode SCLK Falling to LRCK Edge SCLK Falling to SDOUT Valid Base Rate Mode High Rate Mode Notes 8, 9 tr tf tsclkw tsclkw tslrd tdss tdss 1 --------------------( 128 )Fs 1 -----------------( 64 )Fs
50 -
10 10 20
1 (512)Fs 1 (256)Fs
% ns ns ns ns ns ns ns
-20 -
NOTE: When operating the CS53L32A Revision C in Slave Mode, Base Rate Mode, certain timing requirements must be met in addition to those specified above. The required timing relationship between the MCLK and LRCK is shown in Figures 3. An MCLK rising edge cannot lead an LRCK transition by 6ns to 10ns. 8. There must be exactly 32, 48, 64, or 128 SCLK periods per LRCK transition.
9. Slave Mode operation requires an exact 50% duty cycle. Otherwise the CS53L32A will produce erroneous data.
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t sclkh SCLK t sclkl LRCK t dss SDOUT MSB
Figure 1. SCLK to LRCK and SDOUT, Slave Mode
t sclkw
t slrd
SCLK t slrd LRCK t sdo SDOUT MSB MSB-1
Figure 2. SCLK to LRCK and SDOUT, Master Mode
LRCK Input 6 ns 10 ns MCLK Input
No rising edge of MCLK allowed within this timing window.
Figure 3. Relationship Required Between LRCK and MCLK in Slave Mode
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CS53L32A
SWITCHING CHARACTERISTICS - CONTROL PORT - TWO WIRE MODE
(TA = 25 C; VL = 1.7 V - 3.6 V; Inputs: logic 0 = GND, logic 1 = VL, CL = 30 pF)
Parameter Symbol Min Max Unit
Two Wire Mode
SCL Clock Frequency RST Rising Edge to Start Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling SDA Setup time to SCL Rising Rise Time of SCL Fall Time of SCL Rise Time of SDA Fall Time of SDA Setup Time for Stop Condition (Note 10) fscl tirs tbuf thdst tlow thigh tsust thdd tsud trc tfc trd tfd tsusp 500 4.7 4.0 4.7 4.0 4.7 0 250 4.7 100 25 25 1 300 KHz ns s s s s s s ns ns ns us ns s
Note: 10. Data must be held for sufficient time to bridge the transition time, tf, of SCL .
RST RST
t irs t irs Stop
Stop
SDA
Start
Start
Repeated Repeated Start
Start
Stop
Stop
SDA
t buf
t buf
SCL
t hdst
t hdst
t high
t
t high
t
hdst
tf
hdst
tf
t susp
t susp
SCL
t low t hdd t sud t sust tr
t
low
t
hdd
t sud
t sust
tr
Figure 4. Control Port Timing - Two Wire Mode
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SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE
(TA = 25 C; VL = 1.7V - 3.6V; Inputs: logic 0 = GND, logic 1 = VL, CL = 30 pF)
Parameter Symbol Min Max Unit
SPI Mode
CCLK Clock Frequency RST Rising Edge to CS Falling CCLK Edge to CS Falling CS High Time Between Transmissions CS Falling to CCLK Edge CCLK Low Time CCLK High Time CDIN to CCLK Rising Setup Time CCLK Rising to DATA Hold Time Rise Time of CCLK and CDIN Fall Time of CCLK and CDIN (Note 12) (Note 13) (Note 13) (Note 11) fsclk tsrs tspi tcsh tcss tscl tsch tdsu tdh tr2 tf2 500 500 1.0 20 66 66 40 15 6 100 100 MHz ns ns s ns ns ns ns ns ns ns
Notes: 11. tspi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times. 12. Data must be held for sufficient time to bridge the transition time of CCLK. 13. For FSCLK < 1 MHz.
RST
t srs
CS t spi t css CCLK t scl t sch t csh
t r2
CDIN
t f2
t dsu t dh
Figure 5. Control Port Timing - SPI Mode
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CS53L32A
2. TYPICAL CONNECTION DIAGRAM
*Ferrite bead + 1.0 F 0.1 F 5 VA *Ferrite bead + 1.0 F FILT+ 1 VL 0.1 F REF_GND 16 13 0.1 F + 1.0 F
1.8 to 3.3 V Supply
1.8 to 3.3 V Supply
150
0.47 F **
CS53L32A
18 AIN_L1 VQ 19
0.1 F
+ 1.0 F
0.01 F
150
0.47 F **
17 AIN_R1 MCLK LRCK 2 7 3 4 Digital Audio Source
0.01 F
150
0.47 F **
15 AIN_L2
SCLK SDOUT
0.01 F
150
0.47 F **
14 AIN_R2
RST SDA/CDIN/DIF SCL/CCLK/ChSEL AD0/CS/DIV
20 9 10 8 12 11 c/ Mode Configuration
0.01 F
**Optional if analog input circuit is biased within 5% of CS53L32A nominal bias voltage * Optional GND 6
AFLTL AFLTR
1 nF
1 nF
Figure 6. Typical Connection Diagram
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3.
3.1
REGISTER QUICK REFERENCE
** "default" ==> bit status after power-up-sequence or reset.
I/O and Power Control (address 01h)
6 BOOST 0 5 AINMUX1 0 4 AINMUX0 0 3 RESERVED 0 2 RESERVED 0 1 PDN 1 0 CP_EN 0
7 RESERVED 0
BOOST
20 dB Digital Gain Default = `0' 0 - Disabled 1 - Enabled Analog Input Multiplexer Default ='0'. 0 - AIN_L1/AIN_R1 direct to A/D (default) 1 - AIN_L2/AIN_R2 direct to A/D 2 - AIN_L2/AIN_R2 through PGA to A/D 3 - Reserved Power-Down Default ='1'. 0 - Disabled 1 - Enabled Control Port Enable Default ='0'. 0 - Disabled 1 - Enabled
AINMUX
PDN
CP_EN
3.2
Interface Control (address 02h)
6 MCLKDIV 0 5 RATIO1 0 4 RATIO0 0 3 MASTER 0 2 DIF2 0 1 DIF1 0 0 DIF0 0
7 RESERVED 0
MCLKDIV
Master Clock Divider Default ='0'. 0 - Disabled 1 - Enabled Master Clock Ratio Default ='0'. 0 - 128x (default) 1 - 192x 2 - 256x 3 - 384x Master Mode Default ='0'. 0 - Slave Mode 1 - Master Mode
RATIO1-0
MASTER
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DIF2-0 Digital Interface Format Default = `0'. 0 - I2S, up to 24-bit Data, Data valid on positive edge of SLCK (default) 1 - Left Justified, up to 24-bit Data, Data valid on positive edge of SLCK 2 - Reserved 3 - Right Justified, 16-bit Data, Data valid on positive edge of SLCK 4 - Right Justified, 24-bit Data, Data valid on positive edge of SLCK 5 - Right Justified, 18-bit Data, Data valid on positive edge of SLCK 6 - Right Justified, 20-bit Data, Data valid on positive edge of SLCK 7 - Reserved
3.3
Analog I/O Control (address 03h)
6 MUTER 0 5 SOFT 1 4 ZC 1 3 RESERVED 0 2 INDVC 0 1 L=R 0 0 HPFREEZE 0
7 MUTEL 0
MUTEL
Left Channel Mute Default = `0'. 0 - Disabled 1 - Enabled Right Channel Mute Default = `0'. 0 - Disabled 1 - Enabled Soft Digital/Analog Volume Control Default = `1'. 0 - Disabled 1 - Enabled Analog Zero Cross Detection Control Default = `1'. 0 - Disabled 1 - Enabled Independent Volume Control Enable Default = `0'. 0 - Disabled 1 - Enabled Left Channel Volume = Right Channel Volume Default = `0'. 0 - Left channel volume is determined by the left channel volume control registers and right channel volume is determined by the right channel volume control registers. 1 - Left and right channel volumes are determined by the left channel volume control registers and the right channel volume control registers are ignored. High-pass filter freeze Default = `0'. 0 - Disabled 1 - Enabled
MUTER
SOFT
ZC
INDVC
L=R
HPFREEZE
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3.4 3.5 Left Channel Digital Volume Control (address 04h) Right Channel Digital Volume Control (address 05h)
7 VOL7 0 6 VOL6 0 5 VOL5 0 4 VOL4 0 3 VOL3 0 2 VOL2 0 1 VOL1 0 0 VOL0 0
VOL7-0
Volume Default = `0'. (Refer to Table 13)
3.6
Analog Gain Control (address 06h)
7 LVOL3 0 6 LVOL2 0 5 LVOL1 0 4 LVOL0 0 3 RVOL3 0 2 RVOL2 0 1 RVOL1 0 0 RVOL0 0
LVOL3-0
Left Analog Gain Default = `0'. (Refer to Table 14) Right Analog Gain Default = `0'. (Refer to Table 14)
RVOL3-0
3.7
Clip Detection Status (address 07h)
6 RESERVED 0 5 RESERVED 0 4 RESERVED 0 3 RESERVED 0 2 RESERVED 0 1 0 CLIP_L_FLAG CLIP_R_FLAG 0 0
7 RESERVED 0
CLIP_L_FLAG CLIP_R_FLAG
Left Channel Clip Detection Right Channel Clip Detection Default = `0'. 0 - No Clipping Detected 1 - Clipping Detected
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4.
4.1
REGISTER DESCRIPTION
GAIN ENABLE
I/O and Power Control Register (address 01h)
7 RESERVED 6 BOOST 5 AINMUX1 4 AINMUX0 3 RESERVED 2 RESERVED 1 PDN 0 CP_EN
Access:
R/W in Two Wire Mode and write only in SPI.
Default:
0 - Disabled
Function:
Applies a 20 dB digital gain to the input signal, regardless of the input path.
4.2
ANALOG INPUT MULTIPLEXER
I/O and Power Control Register (address 01h)
7 RESERVED 6 BOOST 5 AINMUX1 4 AINMUX0 3 RESERVED 2 RESERVED 1 PDN 0 CP_EN
Access:
R/W in Two Wire Mode and write only in SPI.
Default:
0 - AIN_L1/AIN_R1 direct to A/D
Function:
The analog input multiplexer selects the input channel as well as the input path associated with various gain stages.
AINMUX 0 1 2 3 MODE AIN_L1/AIN_R1 direct to A/D AIN_L2/AIN_R2 direct to A/D AIN_L2/AIN_R2 through PGA to A/D Reserved Table 1. Analog Input Options
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4.3 POWER-DOWN
I/O and Power Control Register (address 01h)
7 RESERVED 6 BOOST 5 AINMUX1 4 AINMUX0 3 RESERVED 2 RESERVED 1 PDN 0 CP_EN
Access:
R/W in Two Wire Mode and write only in SPI.
Default:
1 - Enabled
Function:
The entire device will enter a low-power state whenever this function is activated. The power-down bit defaults to `enabled' on power-up and must be disabled before normal operation will begin. The contents of the control registers are retained when this mode is enabled.
PDN 0 1 MODE Disabled Enabled
Table 2. Power-Down Enable
4.4
CONTROL PORT ENABLE
I/O and Power Control Register (address 01h)
7 RESERVED 6 BOOST 5 AINMUX1 4 AINMUX0 3 RESERVED 2 RESERVED 1 PDN 0 CP_EN
Access:
R/W in Two Wire Mode and write only in SPI.
Default:
0 - Disabled
Function:
The CS53L32A will enter Control Port mode when this bit is enabled. Stand-Alone is the default power up mode. See Section 6.3, Recommended Power-up Sequence, for more details.
CP_EN 0 1 MODE Disabled Enabled
Table 3. Control Port Enable
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4.5 MASTER CLOCK DIVIDE
Interface Control Register (address 02h)
7 RESERVED 6 MCLKDIV 5 RATIO1 4 RATIO0 3 MASTER 2 DIF2 1 DIF1 0 DIF0
Access:
R/W in Two Wire Mode and write only in SPI.
Default:
0 - Disabled
Function:
Divides MCLK by two prior to all other chip circuitry.
MCLKDIV 0 1 MODE Disabled Enabled
Table 4. Master Clock Divide Select
4.6
MASTER CLOCK RATIO
Interface Control Register (address 02h)
7 RESERVED 6 MCLKDIV 5 RATIO1 4 RATIO0 3 MASTER 2 DIF2 1 DIF1 0 DIF0
Access:
R/W in Two Wire Mode and write only in SPI.
Default:
0 - 128x
Function:
Sets the ratio of MCLK to LRCK.
RATIO1,0 0 1 2 3 MCLK/LRCK RATIO (MCLKDIV=0) 128x 192x 256x 384x MCLK/LRCK RATIO (MCLKDIV=1) 256x 384x 512x 768x
Table 5. MCLK/LRCK Ratios
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4.7 MASTER MODE
Interface Control Register (address 02h)
7 RESERVED 6 MCLKDIV 5 RATIO1 4 RATIO0 3 MASTER 2 DIF2 1 DIF1 0 DIF0
Access:
R/W in Two Wire Mode and write only in SPI.
Default:
0 - Slave Mode
Function:
Configures the device for master or slave operation when in Control Port mode.
MASTER 0 1 MODE Slave Mode Master Mode
Table 6. Master/Slave Mode Selection
4.8
DIGITAL INTERFACE FORMAT
Interface Control Register (address 02h)
7 RESERVED 6 MCLKDIV 5 RATIO1 4 RATIO0 3 MASTER 2 DIF2 1 DIF1 0 DIF0
Access:
R/W in Two Wire Mode and write only in SPI.
Default:
0 - Format 0 (I2S, up to 24-bit data, Data valid on positive edge of SCLK)
Function:
The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital Interface Format and the options are detailed in Figures 18 through 21.
DIF2 DIF1 DIF0 DESCRIPTION 0 0 0 I2S, up to 24-bit Data, Data valid on positive edge of SCLK 0 0 1 Left Justified, up to 24-bit Data, Data valid on positive edge of SCLK 0 1 0 Reserved 0 1 1 Right Justified, 16-bit Data, Data valid on positive edge of SCLK 1 0 0 Right Justified, 24-bit Data, Data valid on positive edge of SCLK 1 0 1 Right Justified, 18-bit Data, Data valid on positive edge of SCLK 1 1 0 Right Justified, 20-bit Data, Data valid on positive edge of SCLK 1 1 1 Reserved Table 7. Digital Interface Format Format 0 FIGURE 18
1 2 3 4 5 6 7
19 18 19 20 21 -
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4.9 LEFT/RIGHT CHANNEL MUTE
Analog I/O Control (address 03h)
7 MUTEL 6 MUTER 5 SOFT 4 ZC 3 RESERVED 2 INDVC 1 L=R 0 HPFREEZE
Access:
R/W in Two Wire Mode and write only in SPI.
Default:
0 - Disabled
Function:
Digital mute of the left and right channels.
MUTEL/ MUTER 0 1 MODE
Disabled Enabled
Table 8. Left/Right Channel Mute Enable
4.10
SOFT RAMP AND ZERO CROSS ENABLE
Analog I/O Control Register (address 03h)
7 MUTEL 6 MUTER 5 SOFT 4 ZC 3 RESERVED 2 INDVC 1 L=R 0 HPFREEZE
Access:
R/W in Two Wire Mode and write only in SPI.
Default:
11 - Soft Ramp and Zero Cross enabled
Function: Soft Ramp Enable
Soft Ramp allows level changes, both muting and attenuation, to be implemented via an incremental ramp. Digital volume control is ramped from the current level to the new level at a rate of 1/8 dB per left/right clock period. Analog volume control is ramped in 1 dB steps every 8 left/right clock periods in Base Rate mode, and 1 dB every 16 left/right clock periods in High Rate mode.
Zero Cross Enable
Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a timeout period of 512 sample periods in BRM or 1024 sample periods in HRM (approximately 10.7 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel.
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Soft Ramp and Zero Cross Enable
Soft Ramp and Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur in 1 dB steps and be implemented on a signal zero crossing. The level change will occur after a timeout period of 512 sample periods in BRM or 1024 sample periods in HRM (approximately 10.7 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel.
SOFT/ZC 00 01 10 11 ANALOG VOLUME CONTROL MODES Change volume immediately Change volume at next zero cross time Change volume in 1 dB steps Change volume in 1 dB steps at every zero cross time Table 9. Analog Volume Control
.
SOFT 0 1 DIGITAL VOLUME CONTROL MODES Change volume immediately Change volume in1/8 dB steps Table 10. Digital Volume Control
4.11
INDEPENDENT VOLUME CONTROL ENABLE
Analog I/O Control Register (address 03h)
7 MUTEL 6 MUTER 5 SOFT 4 ZC 3 RESERVED 2 INDVC 1 L=R 0 HPFREEZE
Access:
R/W in Two Wire Mode and write only in SPI.
Default:
0 - Enabled
Function:
When this function is disabled, the AIN_L and AIN_R volume levels are controlled by the Left and Right Volume Control registers and the Independent Analog Gain Control registers are ignored. When this function is enabled, the volume levels are determined by both the Volume Control registers and the Independent Analog Gain Control registers.
INDVC 0 1 MODE
Enabled Frozen
Table 11. Independent Volume Control Enable
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4.12 LEFT CHANNEL VOLUME = RIGHT CHANNEL VOLUME
Analog I/O Control (address 03h)
7 MUTEL 6 MUTER 5 SOFT 4 ZC 3 RESERVED 2 INDVC 1 L=R 0 HPFREEZE
Access:
R/W in Two Wire Mode and write only in SPI.
Default:
0 - Disabled
Function:
When this function is disabled, the left channel volume is determined by the left channel volume control register and right channel volume is determined by the right channel volume control register. When enabled, the left and right channel volumes are determined by the left channel volume control register and the right channel volume control register is ignored.
4.13
HIGH-PASS FILTER FREEZE
Analog I/O Control Register (address 03h)
7 MUTEL 6 MUTER 5 SOFT 4 ZC 3 RESERVED 2 INDVC 1 L=R 0 HPFREEZE
Access:
R/W in Two Wire Mode and write only in SPI.
Default:
0 - Enabled
Function:
The high-pass filter works by continuously subtracting a measure of the dc offset from the output of the decimation filter. If the HPFREEZE bit is taken low during normal operation, the current value of the dc offset is frozen and this dc offset will continue to be subtracted from the conversion result. This feature makes it possible to perform a system calibration by: 1) removing the signal source at the input to the subsystem containing the CS53L32A, 2) running the CS53L32A with the HPFREEZE bit high until the filter settles, approximately one second, 3) taking the HPFREEZE bit low, thus disabling the high-pass filter and freezing the stored dc offset. A system calibration performed in this way will eliminate offsets anywhere in the signal path between the calibration point and the CS53L32A.
HPFREEZE 0 1 MODE Enabled Frozen
Table 12. High-Pass Filter Enable
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4.14 VOLUME CONTROL
Left Channel Volume Control Register (address 04h) Right Channel Volume Control Register (address 05h)
7 VOL7 6 VOL6 5 VOL5 4 VOL4 3 VOL3 2 VOL2 1 VOL1 0 VOL0
Access:
R/W in Two Wire Mode and write only in SPI.
Default:
0 - 0 dB (No attenuation)
Function:
The Volume Control allows the user to alter the signal level in 1 dB increments from +12 to -96 dB, when the INDVC bit is disabled. When INDVC is enabled, the Volume Control can be altered in 1 dB increments from 0 to -96 dB. Volume settings are decoded as shown in Table 13, using a 2's complement code. The volume changes are implemented as dictated by the Soft and Zero Cross bits in the Analog I/O Control register. All volume settings less than -96 dB are equivalent to muting the channel.
Binary Code 00001010 00000111 00000000 11000100 10100110 Decimal Value 12 7 0 -60 -90 Volume Setting +12 dB +7 dB 0 dB -60 dB -90 dB
Table 13. Example Volume Settings
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4.15 LEFT/RIGHT ANALOG GAIN
ADC Independent Analog Gain Control Register (address 06h)
7 LVOL3 6 LVOL2 5 LVOL1 4 LVOL0 3 RVOL3 2 RVOL2 1 RVOL1 0 RVOL0
Access:
R/W in Two Wire Mode and write only in SPI.
Default:
0 - 0 dB (No Gain)
Function:
The level of the left and right analog channels can be adjusted in 1 dB increments as dictated by the Soft Ramp and Zero Cross bits from 0 to +12 dB when routed through the PGA via the AINMUX bits in Control Port mode or the CH_SEL pins in Stand-Alone mode. Levels are decoded as shown in Table 14. Levels above +12 dB are interpreted as +12 dB.
Binary Code 0000 0010 1010 1001 1100 Decimal Value 0 2 6 9 12 Volume Setting 0 dB +2 dB +6 dB +9 dB +12 dB
Table 14. Example Gain Settings
4.16
CLIP DETECTION
Clip Detection Status Register (address 07h)
7 RESERVED 6 RESERVED 5 RESERVED 4 RESERVED 3 RESERVED 2 RESERVED 1 0 CLIP_L_FLAG CLIP_R_FLAG
Access:
Read only in Two Wire Mode and unavailable in SPI.
Default:
0 - No Clipping Detected
Function:
The Clip Flags indicate when there is an over-range condition anywhere in the CS53L32A internal signal path. These bits are "sticky". They constantly monitor the ADC signal path and are set to 1 when an overrange condition occurs. They are reset to 0 when read.
CLIP_L_FLAG CLIP_R_FLAG 0 1 Condition
Signal within normal range Signal is over-range
Table 15. Clip Detection Status Bits
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5. PIN DESCRIPTION
1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 RST VQ AIN_L1 AIN_R1 REF_GND AIN_L2 AIN_R2 FILT+ AFLTL AFLTR Reset Quiescent Voltage Analog Input 1 Left Analog Input 1 Right Reference Ground Analog Input 2 Left Analog Input 2 Right Positive Voltage Reference Anti-Aliasing Capacitor Anti-Aliasing Capacitor
Interface Power VL Master Clock MCLK Serial Clock SCLK Serial Audio Data Out SDOUT Analog Power VA Ground GND Left/Right Clock LRCK AD0/CS/DIV AD0/CS/DIV SDA/CDIN/DIF SDA/CDIN/DIF SCL/CCLK/ChSEL SCL/CCLK/ChSEL
Interface Power Master Clock
1 2
VL (Input) - Digital interface power supply. Typically 1.8 to 3.3 VDC. MCLK (Input) - The master clock frequency must be either 256x, 384x, 512x, 768x or 1024x the input sample rate in Base Rate Mode (BRM) and 128x, 192x, 256x, 384x the input sample rate in High Rate Mode (HRM). Table 16 illustrates several standard audio sample rates and the required master clock frequencies. SCLK (Input/Output) - Clocks the individual bits of the serial data out of the SDOUT pin. The required relationship between the Left/Right clock, serial clock and serial data is defined by the DIF2-0 bytes when in Control Port mode or by the DIF1-0 pins when in Stand-Alone mode. SDOUT (Output) - This pin serves two functions. First: Two's complement MSB-first serial data is output on this pin. The data is clocked out of SDOUT via the serial clock and the channel is determined by the Left/Right clock. The required relationship between the Left/Right clock, serial clock and serial data is defined by the DIF2-0 bytes when in Control Port mode or by the DIF pin when in Stand-Alone mode. Second: In Stand-alone mode, Master/Slave mode selection is determined, at start-up, by a 47 kOhm pull-up/pull-down on this line. A pull-up to VL selects Master mode and a pull-down to GND selects Slave mode. VA (Input) - Analog power supply. Typically 1.8 to 3.3 VDC. GND (Input) - Ground Reference. LRCK (Input/Output) - The Left/Right clock determines which channel is currently being output on the serial audio data line SDOUT. The frequency of the Left/Right clock must be at the input sample rate. The required relationship between the Left/Right clock, serial clock and serial data is defined by the DIF2-0 bytes when in Control Port mode or by the DIF pin when in Stand-Alone mode.
Serial Clock
3
Serial Audio Data Out
4
Analog Power Ground Left/Right Clock
5 6 7
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MCLK (MHz) Sample Rate (kHz) 32 44.1 48 64 88.2 96 HRM 128x 192x 256x* 384x* 256x 384x BRM 512x 768x* 1024x*
4.0960 5.6448 6.1440 8.1920 11.2896 12.2880
6.1440 8.4672 9.2160 12.2880 16.9344 18.4320
8.1920 11.2896 12.2880 16.3840 22.5792 24.5760
12.2880 16.9344 18.4320 24.5760 33.8688 36.8640
8.1920 11.2896 12.2880 -
12.2880 16.9344 18.4320 -
16.3840 22.5792 24.5760 -
24.5760 32.7680 36.8640 -
32.7680 45.1584 49.1520 -
* MCLKDIV = 1 in Control Port mode or DIV= Hi when in Stand-Alone mode
Table 16. Common Clock Frequencies
Address Bit MCLK Divide Enable Serial Control Data I/O
8 8 9
AD0/CS (Control Port Mode) (Input) - In Two Wire mode, AD0 is a chip address bit. CS is used to enable the control port interface in SPI mode. DIV (Stand-Alone Mode) (Input) - When high, the chip will enter High Rate Mode. When this pin is low, the chip will enter Base Rate Mode. SDA/CDIN (Control Port Mode) (Input/Output) - In Two Wire mode, SDA is a data I/O line. CDIN is the input data line for the control port interface in SPI mode. DIF (Stand-Alone Mode) (Input) - The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital Interface Format. DIF 0 1 DESCRIPTION I2S, up to 24-bit data Left Justified, up to 24-bit data
Digital Interface Format
9
Table 17. Digital Interface Format - DIF (Stand-Alone Mode)
Serial Control Interface Clock Channel Select
10 10
SCL/CCLK (Control Port Mode) (Input) - Clocks the serial control data into or from SDA/CDIN/DIF. ChSEL (Stand-Alone Mode) (Input) - The analog data path is determined by the Channel Select bit. These options are detailed in Table 18. ChSEL 0 1 DESCRIPTION Channel 1 directly to A/D Channel 2 with 32dB of gain
Table 18. Channel Select Options
Anti-Aliasing Capacitors
11, 12
AFLTR, AFLTL (Output) - Anti-aliasing capacitors for the left and right channels. An external capacitor is required from AFLTR and AFLTL to ground, as shown in Figure 5. AFLTR and AFLTL are not intended to supply external current, and any current drawn from these pins will alter device performance. FILT+ (Output) - Positive reference for internal sampling circuits. An external capacitor is required from FILT+ to ground, as shown in Figure 6. The recommended value will typically provide 60 dB of PSRR at 1 kHz and 40 dB of PSRR at 60 Hz. FILT+ is not intended to supply external current. FILT+ has a typical source impedance of 250 k and any current drawn from this pin will alter device performance. AIN_R1, AIN_L1, AIN_R2, AIN_L2 (Input) - Channel 1/Channel 2 analog inputs.
Positive Voltage Reference
13
Analog Inputs
14, 15, 17, and 18
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Reference Ground Quiescent Voltage
16 19
REF_GND (Input) - Ground reference for the internal sampling circuits. Must be connected to ground. VQ (Output) - Filter connection for internal A/D converter quiescent reference voltage. A capacitor must be connected from VQ to ground. VQ is not intended to supply external current. VQ has a typical source impedance of 250 k and any current drawn from this pin will alter device performance. RST (Input) - The device enters a low power mode and all internal registers are reset to their default settings, including the control port, when low. When high, the control port becomes operational and the PDN bit must be cleared before normal operation will occur. The control port cannot be accessed when Reset is low.
Reset
20
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CS53L32A
6. APPLICATIONS 6.1 GROUNDING AND POWER SUPPLY DECOUPLING
As with any high resolution converter, the CS53L32A requires careful attention to power supply and grounding arrangements to optimize performance. Figure 6 shows the recommended power arrangement with VA and VL connected to clean supplies. Decoupling capacitors should be located as close to the device package as possible.
6.2
OVERSAMPLING MODES
The CS53L32A operates in one of two oversampling modes. Base Rate Mode supports input sample rates up to 50 kHz while High Rate Mode supports input sample rates up to 100 kHz. See Table 16 for more details.
6.3
RECOMMENDED POWER-UP SEQUENCE
1) Hold RST low until the power supply, master, and left/right clocks are stable. In this state, the control port is reset to its default settings and VQ will remain low. 2) Bring RST high. The device will remain in a low power state with VQ low and will initiate the StandAlone power-up sequence. The control port will be accessible at this time. If control port operation is desired, write the CP_EN bit prior to the completion of the Stand-Alone power-up sequence, approximately 1024 LRCK cycles. Writing this bit will halt the Stand-Alone power-up sequence and initialize the control port to its default settings. The desired register settings can be loaded while keeping the PDN bit set to 1. 3) If Control Port mode is selected via the CP_EN bit, set the PDN bit to 0 which will initiate the powerup sequence, which requires approximately 50 S.
7. CONTROL PORT INTERFACE
The control port is used to load all the internal settings. The operation of the control port may be completely asynchronous with the audio sample rate. However, to avoid potential interference problems, the control port pins should remain static if no operation is required. The control port has 2 modes: SPI and Two Wire. If Two Wire operation is desired, AD0/CS should be tied to VL or GND. If the CS53L32A ever detects a high to low transition on AD0/CS after power-up, SPI mode will be selected.
7.1
SPI MODE
In SPI mode, CS is the CS53L32A chip select signal, CCLK is the control port bit clock, CDIN is the input data line from the microcontroller and the chip address is 0010000. All signals are inputs and data is clocked in on the rising edge of CCLK. All CS53L32A registers are write-only in SPI mode. Figure 7 shows the operation of the control port in SPI mode. To write to a register, bring CS low. The first 7 bits on CDIN form the chip address, and must be 0010000. The eighth bit is a read/write indicator (R/W), which must be low to write. The next 8 bits form the Memory Address Pointer (MAP), which is set to the address of the register that is to be updated. The next 8 bits are the data which will be placed into the register designated by the MAP. The CS53L32A has a MAP auto increment capability, enabled by the INCR bit in the MAP. If INCR is a zero, then the MAP will stay constant for successive writes. If INCR is set to a 1, then MAP will auto increment after each byte is written, allowing block writes of successive registers.
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7.2 TWO WIRE MODE
In Two Wire mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL, with the clock to data relationship as shown in Figure 8. There is no CS pin. Pin AD0 forms the partial chip address and should be tied to VL or GND as required. The upper 6 bits of the 7 bit address field must be 001000. To communicate with the CS53L32A the LSB of the chip address field, which is the first byte sent to the CS53L32A, should match the setting of the AD0 pin. The eighth bit of the address byte is the R/W bit (high for a read, low for a write). If the operation is a write, the next byte is the Memory Address Pointer which selects the register to be read or written. See Section 7.3, Memory Address Pointer (MAP). If the operation is a read, the contents of the register pointed to by the Memory Address Pointer will be output. Setting the auto increment bit in MAP, allows successive reads or writes of consecutive registers. Each byte is separated by an acknowledge bit.
Note: The Two-Wire control port mode is compatible with the I2C protocol.
7.3
MEMORY ADDRESS POINTER (MAP)
7 INCR 0 6 Reserved 0 5 Reserved 0 4 Reserved 0 3 Reserved 0 2 MAP2 0 1 MAP1 0 0 MAP0 0
INCR (Auto MAP Increment Enable) Default = `0'. 0 - Disabled 1 - Enabled MAP0-2 (Memory Address Pointer) Default = `000'.
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CS CCLK CHIP ADDRESS CDIN
0010000
R/W
MAP
MSB
DATA
LSB
byte 1 MAP = Memory Address Pointer
byte n
Figure 7. Control Port Timing, SPI Mode
Note 1 SDA
001000 ADDR AD0 R/W ACK DATA 1-8 ACK DATA 1-8 ACK
SCL Start Stop
Note: If operation is a write, this byte contains the Memory Address Pointer, MAP.
Figure 8. Control Port Timing, Two Wire Mode
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0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (normalized to Fs )
0 -10 -20 Amplitude dB -30 -40 -50 -60 -70 -80 -90 -100 0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0.6
Amplitude dB
Frequency (normalized to Fs)
Figure 9. Base-Rate Stopband Rejection
0 -1 -2 Amplitude dB -4 -5 -6 -7 -8 -9 -10 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55
Amplitude dB
Figure 10. Base-Rate Transition Band
0.3 0.25 0.2 0.15 0.1 0.05 0 -0.05 -0.1 -0.15 -0.2 -0.25 -0.3 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 Frequency (normalized to Fs)
-3
Frequency (normalized to Fs )
Figure 11. Base-Rate Transition Band (Detail)
Figure 12. Base-Rate Passband Ripple
0 -10 -20 Amplitude dB -40 -50 -60 -70 -80 -90 -100 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (normalized to Fs) -30
0 -10 -20 Amplitude dB -30 -40 -50 -60 -70 -80 -90 -100 0.4 0.43 0.46 0.49 0.52 0.55 0.58 0.61 0.64 0.67
Frequency (normalized to Fs)
Figure 13. High-Rate Stopband Rejection
Figure 14. High-Rate Transition Band
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0 -1 -2 Amplitude dB -4 -5 -6 -7 -8 -9 -10 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55 Amplitude dB -3 0.3 0.25 0.2 0.15 0.1 0.05 0 -0.05 -0.1 -0.15 -0.2 -0.25 -0.3 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 Frequency (normalized to Fs)
Frequency (normalized to Fs )
Figure 15. High-Rate Transition Band (Detail)
Figure 16. High-Rate Passband Ripple
150
0.47 F AIN_xx 0.01 F
GND
Figure 17. Line Input Test Circuit
LRCK SCLK
Left Channel
Right Channel
SDATA
MSB -1 -2 -3 -4 -5
+5 +4 +3 +2 +1 LSB
MSB -1 -2 -3 -4
+5 +4 +3 +2 +1 LSB
I2S, up to 24-Bit Data. Data Valid on Rising Edge of SCLK.
Figure 18. CS53L32A Control Port Mode - Serial Audio Format 0 (I2S)
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LRCK SCLK
Left Channel
Right Channel
SDATA
MSB -1 -2 -3 -4 -5
+5 +4 +3 +2 +1 LSB
MSB -1 -2 -3 -4
+5 +4 +3 +2 +1 LSB
Left Justified, up to 24-Bit Data. Data Valid on Rising Edge of SCLK.
Figure 19. CS53L32A Control Port Mode - Serial Audio Format 1
LRCK Right Channel
Left Channel
SCLK
SDATA
15 14 13 12 11 10 9 8 7
65
43
21
0
15 14 13 12 11 10 9
876
5
432
10
Right 32 clocks Justified,
16-Bit Data. Data Valid on Rising Edge of SCLK. SCLK Must Have at Least 32 Cycles per LRCK Period.
Figure 20. CS53L32A Control Port Mode - Serial Audio Format 3
LRCK
Left Channel
Right Channel
SCLK
SDATA
0
23 22 21 20 19 18
765
43210
23 22 21 20 19 18
76543210
32 clocks
Right Justified, 24-Bit Data. Data Valid on Rising Edge of SCLK. SCLK Must Have at Least 48 Cycles per LRCK Period.
Figure 21. CS53L32A Control Port Mode - Serial Audio Format 4
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Right Channel
LRCK
Left Channel
SCLK
SDATA
10
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
32 clocks
Right Justified, 20-Bit Data. Data Valid on Rising Edge of SCLK. SCLK Must Have at Least 40 Cycles per LRCK Period.
Figure 23. CS53L32A Control Port Mode - Serial Audio Format 6
LRCK SCLK
Left Channel
Right Channel
SDATA
MSB -1 -2 -3 -4 -5
+5 +4 +3 +2 +1 LSB
MSB -1 -2 -3 -4
+5 +4 +3 +2 +1 LSB
I2S, up to 24-Bit Data. Data Valid on Rising Edge of SCLK
Figure 24. CS53L32A Stand-Alone Mode - Serial Audio Format 0 (I2S)
LRCK
Left Channel
Right Channel
SCLK
SDATA
1
0
17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
32 clocks
Right Justified, 18-Bit Data. Data Valid on Rising Edge of SCLK. SCLK Must Have at Least 36 Cycles per LRCK Period.
Figure 22. CS53L32A Control Port Mode - Serial Audio Format 5
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LRCK SCLK
Left Channel
Right Channel
SDATA
MSB -1 -2 -3 -4 -5
+5 +4 +3 +2 +1 LSB
MSB -1 -2 -3 -4
+5 +4 +3 +2 +1 LSB
Left Justified, up to 24-Bit Data. Data Valid on Rising Edge of SCLK.
Figure 25. CS53L32A Stand-Alone Mode - Serial Audio Format 1
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8. PARAMETER DEFINITIONS
Total Harmonic Distortion + Noise (THD+N)
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels.
Dynamic Range
The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement to full scale. This technique ensures that the distortion components are below the noise level and do not effect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307.
Interchannel Isolation
A measure of crosstalk between the left and right channels. Measured for each channel at the converter's output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in decibels.
Interchannel Gain Mismatch
The gain difference between left and right channels. Units in decibels.
Gain Error
The deviation from the nominal full scale analog output for a full scale digital input.
Gain Drift
The change in gain value with temperature. Units in ppm/C.
9. REFERENCES
1. "How to Achieve Optimum Performance from Delta-Sigma A/D & D/A Converters" by Steven Harris. Paper presented at the 93rd Convention of the Audio Engineering Society, October 1992. 2. CDB53L32 Evaluation Board Datasheet.
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10.PACKAGE DIMENSIONS
20L TSSOP (4.4 mm BODY) PACKAGE DRAWING
N
D
E11 A2 A1
L
E
A
e b2 SIDE VIEW
123
END VIEW
SEATING PLANE
TOP VIEW
INCHES DIM A A1 A2 b D E E1 e L MIN -0.002 0.03346 0.00748 0.252 0.248 0.169 -0.020 0 NOM -0.004 0.0354 0.0096 0.256 0.2519 0.1732 -0.024 4 MAX 0.043 0.006 0.037 0.012 0.259 0.256 0.177 0.026 0.028 8 MIN -0.05 0.85 0.19 6.40 6.30 4.30 -0.50 0
MILLIMETERS NOM --0.90 0.245 6.50 6.40 4.40 -0.60 4 MAX 1.10 0.15 0.95 0.30 6.60 6.50 4.50 0.65 0.70 8
NOTE
2,3 1 1
JEDEC #: MO-153
Controlling Dimension is Millimeters. Notes: 1. "D" and "E1" are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. Dimension "b" does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of "b" dimension at maximum material condition. Dambar intrusion shall not reduce dimension "b" by more than 0.07 mm at least material condition. 3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.
DS513F1
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CS53L32A
11.CHANGE HISTORY
Table 19. Revision Table Revision Date Change
PP1 PP2 F1
July 2000 September 2004 October 2004
Initial release Added part number CS53L32A-KZZ, lead free package option. Updated Min/Max Specifications Integrated Errata ER513B1 Integrated Errata ER513B2 Integrated Errata ER513C1
Contacting Cirrus Logic Support
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40
DS513F1

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